34 #if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )
57 #define CSEN_REF_VALID(ref) ((ref) == CSEN)
88 void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down)
90 EFM_ASSERT(up < 0x10000);
91 EFM_ASSERT(down < 0x10000);
93 csen->DMBASELINE = (up << _CSEN_DMBASELINE_BASELINEUP_SHIFT)
94 | (down << _CSEN_DMBASELINE_BASELINEDN_SHIFT);
115 void CSEN_Init(CSEN_TypeDef *csen,
const CSEN_Init_TypeDef *init)
119 EFM_ASSERT(CSEN_REF_VALID(csen));
120 EFM_ASSERT(init->warmUpCount < 4);
123 tmp = CSEN_CTRL_STM_DEFAULT;
125 if (init->cpAccuracyHi)
127 tmp |= CSEN_CTRL_CPACCURACY_HI;
130 if (init->localSense)
132 tmp |= _CSEN_CTRL_LOCALSENS_MASK;
137 tmp |= CSEN_CTRL_WARMUPMODE_KEEPCSENWARM;
143 csen->TIMCTRL = (init->warmUpCount << _CSEN_TIMCTRL_WARMUPCNT_SHIFT)
144 | (init->pcReload << _CSEN_TIMCTRL_PCTOP_SHIFT)
145 | (init->pcPrescale << _CSEN_TIMCTRL_PCPRESC_SHIFT);
148 csen->PRSSEL = init->prsSel << _CSEN_PRSSEL_PRSSEL_SHIFT;
151 csen->SCANINPUTSEL0 = (init->input0To7 << _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT)
152 | (init->input8To15 << _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT)
153 | (init->input16To23 << _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT)
154 | (init->input24To31 << _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT);
157 csen->SCANINPUTSEL1 = (init->input32To39 << _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT)
158 | (init->input40To47 << _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT)
159 | (init->input48To55 << _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT)
160 | (init->input56To63 << _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT);
186 void CSEN_InitMode(CSEN_TypeDef *csen,
const CSEN_InitMode_TypeDef *init)
190 EFM_ASSERT(CSEN_REF_VALID(csen));
191 EFM_ASSERT(init->dmIterPerCycle < 0x10);
192 EFM_ASSERT(init->dmCycles < 0x10);
197 tmp = ((uint32_t)init->sampleMode
198 | (uint32_t)init->convSel
199 | (uint32_t)init->cmpMode);
201 tmp |= (init->trigSel << _CSEN_CTRL_STM_SHIFT)
202 | (init->accMode << _CSEN_CTRL_ACU_SHIFT)
203 | (init->sarRes << _CSEN_CTRL_SARCR_SHIFT);
207 tmp |= CSEN_CTRL_DMAEN_ENABLE;
212 tmp |= CSEN_CTRL_DRSF_ENABLE;
217 tmp |= CSEN_CTRL_AUTOGND_ENABLE;
221 tmp |= csen->CTRL & (_CSEN_CTRL_CPACCURACY_MASK
222 | _CSEN_CTRL_LOCALSENS_MASK
223 | _CSEN_CTRL_WARMUPMODE_MASK);
228 csen->EMACTRL = init->emaSample << _CSEN_EMACTRL_EMASAMPLE_SHIFT;
231 csen->CMPTHR = init->cmpThr << _CSEN_CMPTHR_CMPTHR_SHIFT;
234 csen->SINGLECTRL = init->singleSel << _CSEN_SINGLECTRL_SINGLESEL_SHIFT;
237 csen->SCANMASK0 = init->inputMask0;
238 csen->SCANMASK1 = init->inputMask1;
241 tmp = (init->dmRes << _CSEN_DMCFG_CRMODE_SHIFT)
242 | (init->dmCycles << _CSEN_DMCFG_DMCR_SHIFT)
243 | (init->dmIterPerCycle << _CSEN_DMCFG_DMR_SHIFT)
244 | (init->dmDelta << _CSEN_DMCFG_DMG_SHIFT);
246 if (init->dmFixedDelta)
248 tmp |= CSEN_DMCFG_DMGRDIS;
254 csen->ANACTRL = (init->resetPhase << _CSEN_ANACTRL_TRSTPROG_SHIFT)
255 | (init->driveSel << _CSEN_ANACTRL_IDACIREFS_SHIFT)
256 | (init->gainSel << _CSEN_ANACTRL_IREFPROG_SHIFT);
267 void CSEN_Reset(CSEN_TypeDef *csen)
269 EFM_ASSERT(CSEN_REF_VALID(csen));
272 csen->CTRL = _CSEN_CTRL_RESETVALUE;
273 csen->TIMCTRL = _CSEN_TIMCTRL_RESETVALUE;
274 csen->PRSSEL = _CSEN_PRSSEL_RESETVALUE;
275 csen->DATA = _CSEN_DATA_RESETVALUE;
276 csen->SCANMASK0 = _CSEN_SCANMASK0_RESETVALUE;
277 csen->SCANINPUTSEL0 = _CSEN_SCANINPUTSEL0_RESETVALUE;
278 csen->SCANMASK1 = _CSEN_SCANMASK1_RESETVALUE;
279 csen->SCANINPUTSEL1 = _CSEN_SCANINPUTSEL1_RESETVALUE;
280 csen->CMPTHR = _CSEN_CMPTHR_RESETVALUE;
281 csen->EMA = _CSEN_EMA_RESETVALUE;
282 csen->EMACTRL = _CSEN_EMACTRL_RESETVALUE;
283 csen->SINGLECTRL = _CSEN_SINGLECTRL_RESETVALUE;
284 csen->DMBASELINE = _CSEN_DMBASELINE_RESETVALUE;
285 csen->DMCFG = _CSEN_DMCFG_RESETVALUE;
286 csen->ANACTRL = _CSEN_ANACTRL_RESETVALUE;
287 csen->IEN = _CSEN_IEN_RESETVALUE;
288 csen->IFC = _CSEN_IF_MASK;
Clock management unit (CMU) API.
Emlib peripheral API "assert" implementation.
Capacitive Sense Module (CSEN) peripheral API.