CMSIS-SVD  Version 1.3.1
CMSIS System View Description
Device Level

The element device provides the outermost frame of the description.


<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
    <name>identifierType</name>
    <version>xs:string</version>
    <description>xs:string</description>
    <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>
    <width>scaledNonNegativeInteger</width>

    <!-- registerPropertiesGroup -->
    <size>scaledNonNegativeInteger</size>
    <access>accessType</access>
    <resetValue>scaledNonNegativeInteger</resetValue>
    <resetMask>scaledNonNegativeInteger</resetMask>
    <!-- end of registerPropertiesGroup -->

    <peripherals>
        ...
    </peripherals>

    <vendorExtensions>
        ...
    </vendorExtensions>
</device>

Attribute Name Description Type Occurrence
xmlns:xs Specifies the underlying XML schema to which the CMSIS-SVD schema is compliant. Has to be set to: "http://www.w3.org/2001/XMLSchema-instance". xs:decimal 1..1
xmlns:xs Specifies the file path and file name of the CMSIS-SVD Schema. For example, CMSIS-SVD.xsd. xs:string 1..1
schemaVersion Specifies the CMSIS-SVD schema version the description is compliant to (for example, 1.1). xs:decimal 1..1
Element Name Description Type Occurrence
name The name string is used to identify the device or device series. Device names are required to be unique. xs:string 1..1
version The string defines the version of the file. Silicon vendors maintain the description throughout the life-cycle of the device and ensure that all updated and released copies have a unique version string. Higher numbers indicate a more recent version. xs:string 1..1
description String for describing main features of a device (for example CPU, clock frequency, peripheral overview). xs:string 1..1
addressUnitBits Defines the number of data bits uniquely selected by each address. The value for Cortex-M based devices is 8 (byte-addressable). scaledNonNegativeInteger 1..1
width Defines the number of data bit-width of the maximum single data transfer supported by the bus infrastructure. This information is relevant for debuggers when accessing registers, because it might be required to issue multiple accesses for accessing a resource of a bigger size. The expected value for Cortex-M based devices is 32. scaledNonNegativeInteger 1..1
See registerPropertiesGroup for details.
size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
access Defines the default access rights for all registers. accessType 0..1
protection Defines extended access protection for all registers. protectionStringType 0..1
resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
peripherals Next level of description. see Peripherals Level for details.   1..1
vendorExtensions The content and format of this section of the description is unspecified. Silicon vendors may choose to provide additional information. By default, this section is ignored for constructing the CMSIS files. It is up to the silicon vendor to specify a schema for this section. xs:anyType (restriction) 0..1

Example:

<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<name>ARM_Cortex_M3</name>
<version>0.1</version>
<description>ARM Cortex-M3 based Microcontroller demonstration device</description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xffffffff</resetMask>
<peripherals>
...
</peripherals>
</device>

The device description above is at version 0.1 and uniquely identifies the device by the name "ARM_Cortex_M3". The peripherals are memory mapped in a byte-addressable address space with a bus width of 32 bits. The default size of the registers contained in the peripherals is set to 32 bits. Unless redefined for specific peripherals, all registers or fields are read-write accessible. A reset value of 0, valid for all 32 bits as specified by the reset mask, is set for all registers unless redefined at a lower level.